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TC55V16256JI/FTI-12,-15
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 16-BIT CMOS STATIC RAM DESCRIPTION
The TC55V16256JI/FTI is a 4,194,304-bit high-speed static random access memory (SRAM) organized as 262,144 words by 16 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed, it operates from a single 3.3 V power supply. Chip enable ( CE ) can be used to place the device in a low-power mode, and output enable ( OE ) provides fast memory access. Data byte control signals ( LB , UB ) provide lower and upper byte access. This device is well suited to cache memory applications where high-speed access and high-speed storage are required. All inputs and outputs are directly LVTTL compatible. The TC55V16256JI/FTI is available in plastic 44-pin SOJ and 44-pin TSOP with 400mil width for high density surface assembly. The TC55V16256JI/FTI guarantees -40 to 85C operating temperature so it is suitable for use in wide operating temperature system.
FEATURES
* Fast access time (the following are maximum values) TC55V16256JI/FTI-12:12 ns TC55V16256JI/FTI-15:15 ns Low-power dissipation (the following are maximum values)
Cycle Time Operation (max) 12 230 15 200 20 170 25 150 ns mA
*
* * * * * *
Standby:10 mA (both devices)
Single power supply voltage of 3.3 V 0.3 V Fully static operation All inputs and outputs are LVTTL compatible Output buffer control using OE Data byte control using LB (I/O1 to I/O8) and UB (I/O9 to I/O16) Package: SOJ44-P-400-1.27 (JI) (Weight: 1.64 g typ) TSOP II44-P-400-0.80 (FTI) (Weight: 0.45 g typ)
PIN ASSIGNMENT (TOP VIEW)
44 PIN SOJ 44 PIN TSOP
PIN NAMES
A0 to A17 A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VDD GND I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 A16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 GND VDD I/O12 I/O11 I/O10 I/O9 NU A8 A9 A10 A11 A17 A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VDD GND I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 A16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 GND VDD I/O12 I/O11 I/O10 I/O9 NU A8 A9 A10 A11 A17 I/O1 to I/O16
CE
Address Inputs Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input Data Byte Control Inputs Power (+3.3 V) Ground Not Usable (Input)
WE
OE LB , UB
VDD GND NU
(TC55V16256JI)
(TC55V16256FTI)
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BLOCK DIAGRAM
A0 A1 A4 A5 A8 A9 A13 A14 A15 A17
ROW ADDRESS BUFFER
ROW DECODER
MEMORY CELL ARRAY 1,024 x 256 x 16 (4,194,304)
VDD GND
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16
SENSE AMP DATA OUTPUT BUFFER CE COLUMN ADDRESS BUFFER CLOCK GENERATOR A2 A3 A6 A7 A10 A11 A12 A16 VALUE -0.5 to 4.6 -0.5* to 4.6 -0.5* to VDD + 0.5** 1.4 260 -65 to 150 -40 to 100 DATA INPUT BUFFER
COLUMN DECODER
WE
OE UB
LB
CE
CE
MAXIMUM RATINGS
SYMBOL VDD VIN VI/O PD Tsolder Tstg Topr Power Supply Voltage Input Terminal Voltage Input/Output Terminal Voltage Power Dissipation Soldering Temperature (10s) Storage Temperature Operating Temperature RATING UNIT V V V W C C C
*: -1.5 V with a pulse width of 20% tRC min (4 ns max) **: VDD + 1.5 V with a pulse width of 20% tRC min (4 ns max)
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DATA OUTPUT BUFFER
DATA INPUT BUFFER
CE
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DC RECOMMENDED OPERATING CONDITIONS (Ta = -40 to 85C)
SYMBOL VDD VIH VIL PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage MIN 3.0 2.0 -0.3* TYP 3.3 MAX 3.6 VDD + 0.3** 0.8 UNIT V V V
*: -1.0 V with a pulse width of 20% tRC min (4 ns max) **: VDD + 1.0 V with a pulse width of 20% tRC min (4 ns max)
DC CHARACTERISTICS (Ta = -40 to 85C, VDD = 3.3 V 0.3 V)
SYMBOL IIL ILO PARAMETER Input Leakage Current VIN = 0 to VDD (Except NU pin) Output Leakage Current Input Current (NU pin) Output High Voltage
CE = VIH or WE = VIL or OE = VIH, VOUT = 0 to VDD
TEST CONDITION
MIN -1 -1 -1 -1 2.4 VDD - 0.2 tcycle = 12 ns tcycle = 15 ns tcycle = 20 ns tcycle = 25 ns
TYP
MAX 1
UNIT A A A
1 20 1 0.4 0.2 230 200 170 150 55
II (NU)
VIN = 0 to 0.8 V VIN = 0 to 0.2 V IOH = -2 mA IOH = -100 A IOL = 2 mA IOL = 100 A
CE = VIL, IOUT = 0 mA,
VOH
V
VOL
Output Low Voltage
IDDO
Operating Current
OE = VIH,
mA
Other Input = VIH/VIL IDDS1 IDDS2
CE = VIH, Other Input = VIH or VIL
Standby Current
CE = VDD - 0.2 V, Other Input = VDD - 0.2 V or 0.2 V
mA 10
CAPACITANCE (Ta = 25C, f = 1 .0 MHz)
SYMBOL CIN CI/O Note: PARAMETER Input Capacitance Input/Output Capacitance VIN = GND VI/O = GND TEST CONDITION MAX 6 8 UNIT pF pF
This parameter is periodically sampled and is not 100% tested.
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OPERATING MODE
MODE
CE OE
WE
LB L
UB
I/O1 to I/O8 Output High Impedance Output Input High Impedance Input High Impedance
I/O9 to I/O16 Output Output High Impedance Input Input High Impedance High Impedance High Impedance
POWER IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDS
L L H L L H * H *
Read
L
L
H
H L L
Write
L
*
L
H L
L Outputs Disable L Standby * : Don't care Note: H
H * *
H * *
* H *
High Impedance
The NU pin must be left unconnected or tied to GND or a voltage level of less than 0.8 V. You must not apply a voltage of more than 0.8 V to the NU.
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AC CHARACTERISTICS (Ta = -40 to 85C
READ CYCLE
TC55V16256JI/FTI SYMBOL PARAMETER MIN tRC tACC tCO tOE tBA tOH tCOE tOEE tBE tCOD tODO tBD Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Upper Byte, Lower Byte Access Time Output Data Hold Time from Address Change Output Enable Time from Chip Enable Output Enable Time from Output Enable Output Enable Time from Upper Byte, Lower Byte Output Disable Time from Chip Enable Output Disable Time from Output Enable Output Disable Time from Upper Byte, Lower Byte 12 3 3 1 1 -12 MAX 12 12 6 6 7 7 7 MIN 15 4 4 1 1 -15 MAX 15 15 8 8 8 8 8 ns UNIT
(See Note 1)
, VDD = 3.3 V 0.3 V)
WRITE CYCLE
TC55V16256JI/FTI SYMBOL PARAMETER MIN tWC tWP tCW tBW tAW tAS tWR tDS tDH tOEW tODW Write Cycle Time Write Pulse Width Chip Enable to End of Write Upper Byte, Lower Byte Enable to End of Write Address Valid to End of Write Address Setup Time Write Recovery Time Data Setup Time Data Hold Time Output Enable Time from Write Enable Output Disable Time from Write Enable 12 8 10 10 10 0 0 7 0 1 -12 MAX 7 MIN 15 9 12 12 12 0 0 8 0 1 -15 MAX 8 ns UNIT
AC TEST CONDITIONS
PARAMETER Input Pulse Level Input Pulse Rise and Fall Time Input Timing Measurement Reference Level Output Timing Measurement Reference Level Output Load TEST CONDITION 3.0 V/ 0.0 V 2 ns 1.5 V
Fig.1
3.3 V 1200 I/O pin RL = 50 VL = 1.5 V 1.5 V Fig.1 870
I/O pin Z0 = 50
CL = 30 pF
CL = 5 pF
(For tCOE, tOEE, tBE, tCOD, tBD, tODO, tOEW and tODW )
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TIMING DIAGRAMS
READ CYCLE
(See Note 2)
tRC Address tACC tCO
CE
tOH
tOE
OE
tCOD
(See Note 6)
tBA
UB , LB
tODO
(See Note 6)
tBE tOEE DOUT Hi-Z tCOE
(See Note 6)
(See Note 6)
tBD
(See Note 6)
(See Note 6)
VALID DATA OUT INDETERMINATE
Hi-Z INDETERMINATE
WRITE CYCLE 1 ( WE CONTROLLED)
(See Note 5)
tWC tAW Address tAS WE tCW
CE
tWP
tWR
tBW
UB , LB
tODW DOUT (See Note 3) INDETERMINATE
(See Note 6)
tOEW
(See Note 6)
Hi-Z tDS tDH
(See Note 4) INDETERMINATE
DIN
VALID DATA IN
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WRITE CYCLE 2 ( CE CONTROLLED)
(See Note 5)
tWC tAW Address tAS WE tCW
CE
tWP
tWR
tBW
UB , LB
(See Note 6)
tBE
tODW
(See Note 6)
DOUT
Hi-Z
tCOE
(See Note 6)
Hi-Z tDH
INDETERMINATE tDS DIN
VALID DATA IN
WRITE CYCLE 2 ( UB, LB CONTROLLED)
(See Note 5)
tWC tAW Address tAS WE tCW
CE
tWP
tWR
tBW
UB , LB
(See Note 6)
tCOE
tODW
(See Note 6)
DOUT
Hi-Z tBE
(See Note 6)
Hi-Z INDETERMINATE tDS tDH
DIN
VALID DATA IN
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Note: (1) (2) (3) (4) (5) (6) Operating temperature (Ta) is guaranteed for transverse air flow exceeding 400 linear feet per minute. WE remains HIGH for the Read Cycle. If CE goes LOW coincident with or after WE goes LOW, the outputs will remain at high impedance. If CE goes HIGH coincident with or before WE goes HIGH, the outputs will remain at high impedance. If OE is HIGH during the write cycle, the outputs will remain at high impedance. The parameters specified below are measured using the load shown in Fig.1. (A) (B) tCOE, tOEE, tBE, tOEW tCOD, tODO, tBD, tODW Output Enable Time Output Disable Time
CE , OE UB , LB
WE (A) 0.2 V 0.2 V INDETERMINATE (B) 0.2 V DOUT Hi-Z VALID DATA OUT INDETERMINATE Hi-Z 0.2 V
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PACKAGE DIMENSIONS
SOJ44-P-400-1.27
Weight: 1.64 g (typ)
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PACKAGE DIMENSIONS
Weight: 0.45 g (typ)
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RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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